1. Field of the Disclosure
The technology of this disclosure relates generally to voltage level shifting circuits, and specifically to level shifting circuits providing dynamic voltage level shifting.
2. Background
Integrated circuits used in devices where power consumption is a concern may include a plurality of disparate voltage domains. In order for the different voltage domains to interoperate, voltage level shifting circuits may be employed. Generally, level shifting circuits receive a discrete input voltage and translate it to a discrete output voltage.
Level shifting circuits may employ one or more bias voltages in order to facilitate translation from one supply voltage to another. U.S. Pat. No. 7,053,657 illustrates such bias voltages pbias and pbias, substantially reproduced in FIG. 1, which may be distinct from the provided supply voltages Vint and Vext. The use of bias voltage(s) may increase the complexity of the overall design due to the need to generate and distribute the bias voltage(s).
Other conventional level shifting circuits may provide static voltage level shifting. U.S. patent application No. 2007/0188194 illustrates an exemplary static level shifting circuit substantially reproduced in FIG. 2. A signal from a first voltage domain having a voltage supply Vdd appearing at input IN is provided to the level shifting circuit, which produces a level shifted representation of that input in a second voltage domain having a voltage supply Vpp. For some applications, it would be desirable to isolate the output of the level shifter from transitions on the input of the level shifter. For instance, in the case of a write bit line driver circuit in a memory having shared dynamic read and write bit lines, the bit lines may need to be able to decouple from ground (i.e. “float”) so that they can be precharged. A static level shifting circuit coupled to the bit lines would hold the bit lines in complementary logic states and would propagate any changes on the data input to the bit lines, which could interfere with read and write operations in the memory.